1. Field of the Invention
This invention relates to the field of integrated circuits. More particularly, this invention relates to the field of clock generators for a memory within an integrated circuit.
2. Description of the Prior Art
Clock signal generation for controlling memories within integrated circuits is a critical design challenge when seeking to obtain high speed performance coupled with low power consumption. It is known to use self-timed memories in which a clock pulse is generated triggered by one edge of a source clock signal and having a duration controlled by a model delay line seeking to represent the signal processing paths within the memory concerned. The principle of operation of such circuits is that variations in the speed of operation of the memory circuits, such as due to process, voltage and temperature fluctuations, will result in corresponding changes in the speed of operation of the delay lines modelling the memory behaviour and accordingly an appropriate adjustment will be made in the pulse duration such that the pulse will terminate at an appropriate time. If the pulse is too short, then the read operation may not have properly completed at the point at which the bit value is captured from the memory. Conversely, if the pulse is too long, then the voltage swinging on the bit lines in the memory may be unnecessarily large resulting in an unnecessary increase in energy consumed as well as the read speed being unnecessarily slowed.
An increasing trend within integrated circuits, including those incorporating memories, is to operate at lower voltages. Such lower voltages significantly reduce power consumption. However, lower operating voltages present additional challenges in the field of integrated circuit memories. Bit storage cells within memories are typically provided in the form of circuits using feedback to maintain a particular signal level representing either a “0” or a “1”. In order to write a new bit value into such a storage location, a voltage needs to be applied which will overcome the feedback being used within the bit storage cell and accordingly impress the new signal value into that bit storage cell for subsequent maintenance by the feedback mechanism when the write value is no longer being driven into the bit storage cell. However, with the use of lower operating voltages there is a reduction in the margin associated with the write signal being able to overcome the feedback mechanisms within the bit storage cells. Furthermore, as device sizes tend to decrease, the variation in the characteristics of individual bit storage cells with variations in process, voltage and temperature which occur can have the result that bit cells may not be properly written as the write signal may not be able to overpower the feedback within the bit storage cell in the time provided by the memory clock signal (or at all).
One way of dealing with this problem would be to increase the pulse duration of the self-timed memory clocks to increase the time available for the write operation to be completed. However, this has the disadvantage that during a read operation such an excessively long pulse duration will result in the bit lines being unnecessarily discharged for a longer duration until read by the sense amplifiers. This will increase the power consumption of the memory in a disadvantageous manner. Furthermore, the process, voltage and temperature variations which alter the characteristics of the memory can also alter the performance characteristics of the clock generator. These variations in the clock generator characteristics may result in changes in the pulse duration opposite to the requirements for changes in the pulse duration which arise due to the same variations occurring within the memory. Thus, a change requiring a longer pulse duration for correction operation of the memory may in fact cause the clock generator to vary its performance in a way which actually reduces the pulse duration.
One way of dealing with this problem would be to adopt a memory clock which has its characteristics, i.e. its rising and falling edges, determined by a source clock signal from which it is derived. A source clock signal can be generated by a circuit such as a phase-locked-loop circuit and produce a source clock signal which is resistant to changes in process, voltage and temperature. Thus, by generating the memory clock signal in response to both the rising and falling edges of the source clock signal, the memory clock signal can be made to have more stable characteristics. Thus, such a memory clock signal can be used to control write operations in a manner in which the write operation will be assured to last for more than a known amount of time to help ensure that the feedback characteristics of bit storage cells will be overcome and a new data value will be properly written therein. However, such an approach to generating the memory clock signal has the result that it is no longer possible to obtain the performance and power consumption advantages associated with the self-timed type of memory clock signal generation. The type of memory clock signal derived from both rising and falling edges of a source clock signal will not be able to track the normal variations in process, voltage and temperature as is normally the case with such self-timed clocks. Thus, the integrated circuit memory will normally have to be configured with worst-case design assumptions in mind resulting in lower performance and higher power consumption.